Online Access Free H13-231-ENU Practice Test

Which of the following statements about the RISC instruction set architecture is wrong?

• A.RISC CPU contains abundant circuit units. Therefore, the function is strong, the area is large, and the power consumption is large.
• B.When implementing special functions on RISC machines, the efficiency may be low.
• C.RISC designers focus on the frequently used instructions and try to make them simple and efficient.
• D.RISC assembly language programs generally require larger memory space. When implementing special functions, the program is complicated and difficult to design.

Which of the following statements about RAID50 is correct?

• A.The disk utilization of RAID50 is (N-M/N (N is the number of RAID member disks, M is the number of subgroups of RAID)
• B.RAID50 is extremely reliable and can tolerate up to 4 disk failures.
• C.The read and write performance of RAID50 is average.
• D.RAID50 is a two-level combination of RAID5 and RAID0. RAID0 first, then RAID5

A company wants to migrate a java program under the original X86 platform Linux to the kunpeng platform. EulerOS has been installed on the TaiShan server. Which of the following commands can implement?

• A.yum install java-1.8.0-openjdk.
• B.apt-get update java-1.8.0-openjdk.
• C.apt-get install java-1.8.0-openjdk.
• D.yum update java-1.8.0-openjdk.

Which of the following is correct about the characteristics of heterogeneous computing? (Multiple choice)

• A.Common heterogeneous system architectures include CPU+GPU, GPU+FPGA, CPU+special chip.
• B.GPU and CPU work together to form a heterogeneous computing system. The advantages of the heterogeneous computing system are computing acceleration and energy saving.
• C.The purpose of heterogeneous computing is mainly to solve the problem of insufficient CPU computing power.
• D.Heterogeneous computing is to develop a series of software and hardware standards, so that different types of computing devices can share the process and results of computing.

Huawei's latest generation of smart SSD control chip. Which of the following features include? (Multiple choice)

• A.Super wear algorithm, life extension 20%
• B.16nm process technology
• C.Fusion of PCIe NVMe and SAS
• D.Support PCIe hot plug and smart acceleration